NU - EECS - 13 - 03 April 10 , 2013 VMM - based Emulation of Intel Hardware Transactional Memory

We describe the design, implementation, and evaluation of emulated hardware transactional memory, specifically the Intel Haswell Restricted Transactional Memory (RTM) architectural extensions for x86/64, within a virtual machine monitor (VMM). Our system allows users to investigate RTM on hardware that does not provide it, debug their RTM-based transactional software, and stress test it on diverse emulated hardware configurations. We are able to accomplish this approximately 60 times faster than under emulation. A noteworthy aspect of our system is a novel page-flipping technique that allows us to completely avoid instruction emulation, and to limit instruction decoding to only that necessary to determine instruction length. This makes it possible to implement RTM emulation, and potentially other techniques, far more compactly than would otherwise be possible. We have implemented our system in the context of the Palacios VMM. Our techniques are not specific to Palacios, and could be implemented in other VMMs. This project is made possible by support from the United States National Science Foundation (NSF) via grant CNS0709168, and the Department of Energy (DOE) via grant DE-SC0005343.